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general description the max1533/MAX1537 are dual step-down, switch- mode power-supply (smps) controllers with synchro- nous rectification, intended for main 5v/3.3v power generation in battery-powered systems. fixed-frequen- cy operation with optimal interleaving minimizes input ripple current from the lowest input voltages up to the 26v maximum input. optimal 40/60 interleaving allows the input voltage to go down to 8.3v before duty-cycle overlap occurs, compared to 180 out-of-phase regula- tors where the duty-cycle overlap occurs when the input drops below 10v. output current sensing pro- vides accurate current limit using a sense resistor. alternatively, power dissipation can be reduced using lossless inductor current sensing. internal 5v and 3.3v linear regulators power the max1533/MAX1537 and their gate drivers, as well as external keep-alive loads, up to a total of 100ma. when the main pwm regulators are in regulation, automatic bootstrap switches bypass the internal linear regulators, providing currents up to 200ma from each linear output. an additional 5v to 23v adjustable internal 150ma linear regulator is typically used with a secondary winding to provide a 12v supply. the max1533/MAX1537 include on-board power-up sequencing, a power-good (pgood) output, digital soft-start, and internal soft-shutdown output discharge that prevents negative voltages on shutdown. the max1533 is available in a 32-pin 5mm x 5mm thin qfn package, and the MAX1537 is available in a 36-pin 6mm x 6mm thin qfn package. the exposed backside pad improves thermal characteristics for demanding linear keep-alive applications. applications 2 to 4 li+ cells battery-powered devices notebook and subnotebook computers pdas and mobile communicators features ? fixed-frequency, current-mode control ? 40/60 optimal interleaving ? accurate differential current-sense inputs ? internal 5v and 3.3v linear regulators with 100ma load capability ? auxiliary 12v or adjustable 150ma linear regulator (MAX1537 only) ? dual-mode feedback?.3v/5v fixed or adjustable output (dual mode) voltages ? 200khz/300khz/500khz switching frequency ? versatile power-up sequencing ? adjustable overvoltage and undervoltage protection ? 6v to 26v input range ? 2v ?.75% reference output ? power-good output ? soft-shutdown ? 5? (typ) shutdown current max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ________________________________________________________________ maxim integrated products 1 32 31 30 29 28 27 26 9 101112131415 18 19 20 21 22 23 24 7 6 5 4 3 2 1 max1533 thin qfn 5mm x 5mm top view on3 on5 fsel ilim3 ilim5 ref gnd 8 v cc shdn dh5 bst5 lx5 in csh5 25 csl5 fb5 ldo5 dl5 pgnd dl3 ldo3 fb3 17 csl3 ovp lx3 16 csh3 bst3 dh3 uvp pgood pgdly skip pin configurations ordering information part temp range pin-package max1533 etj -40? to +85? 32 thin qfn 5mm x 5mm max1533etj+ -40? to +85? 32 thin qfn 5mm x 5mm MAX1537 etx -40? to +85? 36 thin qfn 6mm x 6mm MAX1537etx+ -40? to +85? 36 thin qfn 6mm x 6mm 19-3501; rev 0; 11/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available dual mode is a trademark of maxim integrated products, inc. pin configurations continued at end of data sheet. + denotes lead-free package.
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v in = 12v, both smps enabled, v cc = 5v, fsel = ref, skip = gnd, v ilim_ = v ldo5 , v ina = 15v, v ldoa = 12v, i ldo5 = i ldo3 = i ldoa = no load, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, shdn , ina, ldoa to gnd ...............................-0.3v to +30v gnd to pgnd .......................................................-0.3v to +0.3v ldo5, ldo3, v cc to gnd .......................................-0.3v to +6v ilim3, ilim5, pgdly to gnd...................................-0.3v to +6v csl3, csh3, csl5, csh5 to gnd ..........................-0.3v to +6v on3, on5, fb3, fb5 to gnd ..................................-0.3v to +6v skip , ovp , uvp to gnd...........................................-0.3v to +6v pgood, fsel, adja, ona to gnd ........................-0.3v to +6v ref to gnd ................................................-0.3v to (v cc + 0.3v) dl3, dl5 to pgnd..................................-0.3v to (v ldo5 + 0.3v) bst3, bst5 to pgnd .............................................-0.3v to +36v lx3 to bst3..............................................................-6v to +0.3v dh3 to lx3 ..............................................-0.3v to (v bst3 + 0.3v) lx5 to bst5..............................................................-6v to +0.3v dh5 to lx5 ..............................................-0.3v to (v bst5 + 0.3v) ldo3, ldo5 short circuit to gnd .............................momentary ref short circuit to gnd ...........................................momentary ina shunt current.............................................................+15ma continuous power dissipation (t a = +70?) 32-pin tqfn (derate 21.3mw/? above +70?) .......1702mw 36-pin tqfn (derate 26.3mw/? above +70?) .......2105mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units input supplies (note 1) ldo5 in regulation 6 26 v in input voltage range v in in = ldo5, v out5 < 4.43v 4.5 5.5 v v in operating supply current i in ldo5 switched over to csl5 15 35 ? v in standby supply current i in ( stby ) v in = 6v to 26v, both smps off, includes i shdn v in s s i in shdn v in v v shdn = gnd 5 17 a quiescent power consumption p q both smps on, fb3 = fb5 = skip = gnd, v csl3 = 3.5v, v csl5 = 5.3v, v ina = 15v, i ldoa = 0, p in + p csl3 + p csl5 + p ina 3.5 4.5 mw v cc quiescent supply current i cc both smps on, fb3 = fb5 = gnd, v csl3 = 3.5v, v csl5 = 5.3v 1.1 2.1 ma main smps controllers 3.3v output voltage in fixed mode v out3 v in = 6v to 26v, skip = v cc (note 2) 3.280 3.33 3.380 v 5v output voltage in fixed mode v out5 v in = 6v to 26v, skip = v cc (note 2) 4.975 5.05 5.125 v feedback voltage in adjustable mode v fb_ v in = 6v to 26v, fb3 or fb5, duty factor = 20% to 80% (note 2) 0.990 1.005 1.020 v output-voltage adjust range either smps 1.0 5.5 v fb3, fb5 dual-mode threshold 0.1 0.2 v feedback input leakage current v fb3 = v fb5 = 1.1v -0.1 +0.1 ? dc load regulation either smps, skip = v cc , i load = 0 to full load -0.1 %
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, v cc = 5v, fsel = ref, skip = gnd, v ilim_ = v ldo5 , v ina = 15v, v ldoa = 12v, i ldo5 = i ldo3 = i ldoa = no load, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units line-regulation error either smps, duty cycle = 10% to 90% 1 % fsel = gnd 170 200 230 fsel = ref 270 300 330 operating frequency (note 1) f osc fsel = v cc 425 500 575 khz fsel = gnd 91 93 fsel = ref 91 93 maximum duty factor (note 1) d max fsel = v cc 91 93 % minimum on-time t on ( min ) (note 3) 200 ns 40 % smps3 to smps5 phase shift smps5 starts after smps3 144 deg current limit ilim_ adjustment range 0.5 v ref v current-sense input range csh_, csl_ 0 5.5 v current-sense input leakage current csh_, v csh _ = 5.5v -1 +1 ? current-limit threshold (fixed) v limit _v csh _ - v csl _ , ilim_ = v cc 70 75 80 mv v ilim _ = 2.00v 170 200 230 v ilim _ = 1.00v 91 100 109 current-limit threshold (adjustable) v limit _ v csh _ - v csl _ v ilim _ = 0.50v 42 50 58 mv current-limit threshold (negative) v neg v csh_ - v csl_ , skip = v cc , percent of current limit -120 % current-limit threshold (zero crossing) v zx v pgnd - v lx _, skip = gnd, ilim_ = v cc 3mv ilim_ = v cc 10 16 22 mv idle-mode ? threshold v idle v csh _ - v csl _ with respect to current- limit threshold (v limit ) 20 % ilim_ leakage current ilim3 = ilim5 = gnd or v cc -0.1 +0.1 ? soft-start ramp time t ss measured from the rising edge of on_ to full scale 512 / f osc s internal fixed linear regulators ldo5 output voltage v ldo5 on3 = on5 = gnd, 6v < v in < 26v, 0 < i ldo5 < 100ma 4.80 4.95 5.10 v ldo5 undervoltage-lockout fault threshold rising edge, hysteresis = 1% 3.75 4.0 4.25 v ldo5 bootstrap switch threshold rising edge of csl5, hysteresis = 1% 4.41 4.75 v ldo5 bootstrap switch resistance ldo5 to csl5, v csl5 = 5v, i ldo5 = 50ma 0.75 3 ? idle mode is a trademark of maxim integrated products, inc.
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, v cc = 5v, fsel = ref, skip = gnd, v ilim_ = v ldo5 , v ina = 15v, v ldoa = 12v, i ldo5 = i ldo3 = i ldoa = no load, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units ldo3 output voltage v ldo3 standby mode, 6v < v in < 26v, 0 < i load < 100ma 3.20 3.35 3.42 v ldo3 bootstrap switch threshold rising edge of csl3, hysteresis = 1% 2.83 3.10 v ldo3 bootstrap switch resistance ldo3 to csl3, v csl3 = 3.2v, i ldo3 = 50ma 13 ? short-circuit current ldo3 = ldo5 = gnd, csl3 = csl5 = gnd 150 220 ma short-circuit current (switched over to csl_) ldo3 = ldo5 = gnd, v csl3 > 3.1v, v csl5 > 4.7v 250 ma auxiliary linear regulator (MAX1537 only) ldoa voltage range v ldoa 523v ina voltage range v ina 624v ldoa regulation threshold, internal feedback adja = gnd, 0 < i ldoa < 120ma, v ina > 13v 11.4 12.0 12.4 v adja regulation threshold, external feedback v adja 0 < i ldoa < 120ma, v ldoa > 5.0v and v ina > v ldoa + 1v 1.94 2.00 2.06 v adja dual-mode threshold 0.1 0.15 0.2 v adja leakage current v adja = 2.1v -0.1 +0.1 ? ldoa current limit v ldoa forced to v ina - 1v, v adja = 1.9v, v ina > 6v 150 ma secondary feedback regulation threshold v ina - v ldoa 0.65 0.8 0.95 v dl duty factor v ina - v ldoa < 0.7v, pulse width with respect to switching period 33 % ina quiescent current i ina v ina = 24v, i ldoa = no load 50 165 ? ina shunt sink current v ina = 28v 10 ma ina leakage current i ina ( shdn ) v ina = 5v, ldoa disabled 30 ? reference (ref) reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.985 2.00 2.015 v reference load regulation i ref = -10? to +100? 1.980 2.020 v ref lockout voltage v ref ( uvlo ) rising edge, hysteresis = 350mv 1.95 v fault detection output overvoltage trip threshold ovp = gnd, with respect to error- comparator threshold 81115% output overvoltage fault- propagation delay t ovp 50mv overdrive 10 ?
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, v cc = 5v, fsel = ref, skip = gnd, v ilim_ = v ldo5 , v ina = 15v, v ldoa = 12v, i ldo5 = i ldo3 = i ldoa = no load, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units output undervoltage-protection trip threshold with respect to error-comparator threshold 65 70 75 % output undervoltage fault- propagation delay t uvp 50mv overdrive 10 ? output undervoltage-protection blanking time t blank from rising edge of on_ 6144 / f osc s pgood lower trip threshold with respect to error-comparator threshold, hysteresis = 1% -14 -10 -7.5 % pgood propagation delay t pgood _ falling edge, 50mv overdrive 10 s pgood output low voltage i sink = 4ma 0.4 v pgood leakage current i pgood _ high state, pgood forced to 5.5v 1 a pgdly pullup current pgdly = gnd 4 5 6 ? pgdly pulldown resistance 10 25 ? pgdly trip threshold ref- 0.2 ref ref+ 0.2 v thermal-shutdown threshold t shdn hysteresis = 15 c +160 c gate drivers dh_ gate-driver on-resistance r dh bst_ - lx_ forced to 5v 1.5 5 ? dl_, high state 1.7 5 dl_ gate-driver on-resistance r dl dl_, low state 0.6 3 ? dh_ gate-driver source/sink current i dh dh_ forced to 2.5v, bst_ - lx_ forced to 5v 2a dl_ gate-driver source current i dl dl_ forced to 2.5v 1.7 a dl_ gate-driver sink current i dl ( sink ) dl_ forced to 2.5v 3.3 a dl_ rising 35 dead time t dead dh_ rising 26 ns lx_, bst_ leakage current v bst _ = v lx _ = 26v <2 20 ? inputs and outputs high 2.4 logic input voltage skip , hysteresis = 600mv low 0.8 v high 0.7 x v cc fault enable logic input voltage ovp , uvp , ona low 0.4 v logic input current ovp , uvp , skip , ona -1 +1 ? rising trip level 1.10 1.6 2.20 shdn input trip level falling trip level 0.96 1 1.04 v clear fault level/smps off level 0.8 delay start level (ref) 1.9 2.1 on_ input voltage smps on level 2.4 v
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, v cc = 5v, fsel = ref, skip = gnd, v ilim_ = v ldo5 , v ina = 15v, v ldoa = 12v, i ldo5 = i ldo3 = i ldoa = no load, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) electrical characteristics (circuit of figure 1, v in = 12v, both smps enabled, v cc = 5v, fsel = ref, skip = gnd, v ilim_ = v ldo5 , v ina = 15v, v ldoa = 12v, i ldo5 = i ldo3 = i ldoa = no load, t a = -40? to +85? , unless otherwise noted.) (note 4) parameter symbol conditions min typ max units high v cc - 0.2 ref 1.7 2.3 fsel three-level input logic gnd 0.4 v ovp , uvp , skip , ona, on3, on5 = gnd or v cc -1 +1 shdn , 0v or 26v -1 +1 input leakage current fsel = gnd or v cc -3 +3 ? csl_ discharge-mode on-resistance r discharge 10 25 ? csl_ synchronous-rectifier discharge-mode turn-on level 0.2 0.3 0.4 v parameter symbol conditions min max units input supplies (note 1) ldo5 in regulation 6 26 v in input voltage range v in in = ldo5, v out5 < 4.4v 4.5 5.5 v v in operating supply current i in ldo5 switched over to csl5, either smps on 35 ? v in standby supply current i in ( stby ) v in = 6v to 26v, both smps off, includes i shdn 170 ? v in shutdown supply current i in ( shdn ) v in = 6v to 26v 17 ? quiescent power consumption p q both smps on, fb3 = fb5 = skip = gnd, v csl3 = 3.5v, v csl5 = 5.3v, v ina = 15v, i ldoa = 0, p in + p csl3 + p csl5 + p ina 4.5 mw v cc quiescent supply current i cc both smps on, fb3 = fb5 = gnd, v csl3 = 3.5v, v csl5 = 5.3v 2.5 ma main smps controllers 3.3v output voltage in fixed mode v out3 v in = 6v to 26v, skip = v cc (note 2) 3.28 3.38 v 5v output voltage in fixed mode v out5 v in = 6v to 26v, skip = v cc (note 2) 4.975 5.125 v feedback voltage in adjustable mode v fb3 , v fb5 v in = 6v to 26v, fb3 or fb5, duty factor = 20% to 80% (note 2) 0.982 1.018 v output-voltage adjust range either smps 1.0 5.5 v fb3, fb5 adjustable-mode threshold voltage dual-mode comparator 0.1 0.2 v
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, v cc = 5v, fsel = ref, skip = gnd, v ilim_ = v ldo5 , v ina = 15v, v ldoa = 12v, i ldo5 = i ldo3 = i ldoa = no load, t a = -40? to +85? , unless otherwise noted.) (note 4) parameter symbol conditions min max units fsel = gnd 170 230 fsel = ref 240 330 operating frequency (note 1) f osc fsel = v cc 375 575 khz fsel = gnd 91 fsel = ref 91 maximum duty factor (note 1) d max fsel = v cc 91 % minimum on-time t on ( min ) 250 ns current limit ilim_ adjustment range 0.5 v ref v current-limit threshold (fixed) v limit _ v csh _ - v csl _ , ilim_ = v cc 67 83 mv v ilim _ = 2.00v 170 230 v ilim _ = 1.00v 90 110 current-limit threshold (adjustable) v limit _ v csh _ - v csl _ v ilim _ = 0.50v 40 60 mv internal fixed linear regulators ldo5 output voltage v ldo5 on3 = on5 = gnd, 6v < v in < 26v, 0 < i ldo5 < 100ma 4.8 5.1 v ldo5 undervoltage-lockout fault threshold rising edge, hysteresis = 1% 3.75 4.30 v ldo3 output voltage v ldo3 standby mode, 6v < v in < 28v, 0 < i load < 100ma 3.20 3.43 v auxiliary linear regulator (MAX1537 only) ldoa voltage range v loda 523v ina voltage range v ina 624v ldoa regulation threshold, internal feedback adja = gnd, 0 < i ldoa < 120ma, v ina > 13v 11.40 12.55 v adja regulation threshold, external feedback v adja 0 < i ldoa < 120ma, v ldoa > 5.0v and v ina > v ldoa + 1v 1.94 2.08 v adja dual-mode threshold adja 0.10 0.25 v secondary feedback regulation threshold v ina - v ldoa 0.63 0.97 v ina quiescent current i ina v ina = 24v, i ldoa = no load 165 ? reference (ref) reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.97 2.03 v
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 8 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, both smps enabled, v cc = 5v, fsel = ref, skip = gnd, v ilim_ = v ldo5 , v ina = 15v, v ldoa = 12v, i ldo5 = i ldo3 = i ldoa = no load, t a = -40? to +85? , unless otherwise noted.) (note 4) parameter symbol conditions min max units fault detection output overvoltage trip threshold ovp = gnd, with respect to error- comparator threshold +8 +15 % output undervoltage-protection trip threshold with respect to error-comparator threshold +65 +75 % pgood lower trip threshold with respect to error-comparator threshold, hysteresis = 1% -14.0 -7.0 % pgood output low voltage i sink = 4ma 0.4 v pgdly pulldown resistance 25 ? pgdly trip threshold ref- 0.2 ref+ 0.2 v gate drivers dh_ gate-driver on-resistance r dh bst_ - lx_ forced to 5v 5 ? dl_, high state 5 dl_ gate-driver on-resistance r dl dl_, low state 3 ? inputs and outputs high 2.4 logic input voltage skip , hysteresis = 600mv low 0.8 v high 0.7 x v cc fault enable logic input voltage ovp , uvp , ona low 0.4 v rising trip level 1.1 2.2 shdn input trip level falling trip level 0.95 1.05 v clear fault level 0.8 smps off level 1.6 delay start level (ref) 1.9 2.1 on_ input voltage smps on level 2.4 v high v cc - 0.2 ref 1.7 2.3 fsel three-level input logic gnd 0.4 v note 1: the max1533/MAX1537 cannot operate over all combinations of frequency, input voltage (v in ), and output voltage. for large input-to-output differentials and high-switching frequency settings, the required on-time may be too short to maintain the regulation specifications. under these conditions, a lower operating frequency must be selected. the minimum on-time must be greater than 150ns, regardless of the selected switching frequency. on-time and off-time specifications are mea- sured from 50% point to 50% point at the dh_ pin with lx_ = gnd, v bst_ = 5v, and a 250pf capacitor connected from dh_ to lx_. actual in-circuit times may differ due to mosfet switching speeds. note 2: when the inductor is in continuous conduction, the output voltage has a dc regulation level lower than the error-comparator threshold by 50% of the ripple. in discontinuous conduction ( skip = gnd, light load), the output voltage has a dc regula- tion level higher than the trip level by approximately 1% due to slope compensation. note 3: specifications are guaranteed by design, not production tested. note 4: specifications to -40 c are guaranteed by design, not production tested.
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers _______________________________________________________________________________________ 9 pwm5 efficiency vs. load current (v out5 = 5.0v) max1533 toc01 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 0.01 10 v in = 20v v in = 12v v in = 7v skip = gnd skip = v cc 5v output voltage (out5) vs. load current max1533/37 toc02 load current (a) output voltage (v) 45 23 1 4.96 5.00 5.04 5.08 5.12 4.88 4.92 06 skip = gnd skip = v cc 5v output voltage (out5) vs. input voltage max1533/37 toc03 input voltage (v) output voltage (v) 25 15 20 10 4.96 5.00 5.04 5.08 5.12 4.88 4.92 530 skip = gnd skip = v cc no load pwm3 efficiency vs. load current (v out3 = 3.3v) max1533/37 toc04 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 0.01 10 v in = 20v v in = 12v v in = 5v skip = gnd skip = v cc 3.3v output voltage (out3) vs. load current max1533/37 toc05 load current (a) output voltage (v) 45 23 1 3.27 3.30 3.33 3.36 3.39 3.21 3.24 06 skip = gnd skip = v cc 3.3v output voltage (out3) vs. input voltage max1533/37 toc06 input voltage (v) output voltage (v) 25 15 20 10 3.27 3.30 3.33 3.36 3.39 3.21 3.24 530 skip = gnd skip = v cc no load no-load supply current vs. input voltage (fully enabled) max1533/37 toc07 input voltage (v) supply current (ma) 25 15 20 10 16 20 24 28 32 0 12 8 4 05 30 skip = gnd skip = v cc on3 = on5 = v cc 0.22ma (v in = 12v) no-load supply current vs. input voltage (standby mode) max1533/37 toc08 input voltage (v) standby supply current (ma) 25 15 20 10 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.3 0.2 0.1 05 30 on3 = on5 = gnd shutdown supply current vs. input voltage max1533/37 toc09 input voltage (v) shutdown supply current ( a) 25 15 20 10 2 4 6 8 10 0 05 30 shdn = gnd typical operating characteristics (MAX1537 circuit of figure 1, v in = 12v, ldo5 = v cc = 5v, skip = gnd, fsel = ref, t a = +25?, unless otherwise noted.)
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 10 ______________________________________________________________________________________ typical operating characteristics (continued) (MAX1537 circuit of figure 1, v in = 12v, ldo5 = v cc = 5v, skip = gnd, fsel = ref, t a = +25?, unless otherwise noted.) idle-mode current vs. input voltage max1533/37 toc10 input voltage (v) peak current (a) 25 15 20 10 1.5 1.0 0.5 2.0 2.5 3.0 3.5 0 05 30 duty cycle limited 5v output 2.0v reference load regulation max1533 toc11 ref load current ( a) ref voltage (v) 80 60 0 20 40 1.99 2.00 2.01 2.02 1.98 -20 100 linear-regulator load regulation max1533/37 toc12 ldo load current (ma) ldo deviation voltage (mv) 120 100 80 60 40 20 -150 -100 -50 0 50 -200 0 140 ldo3 ldo5 v in = 6v on3 = on5 = gnd auxiliary linear-regulator load regulation max1533/37 toc13 ldoa load current (ma) aux ldo voltage (v) 160 120 80 40 11.8 11.9 12.0 12.1 11.7 0200 interleaved operation max1533/37 toc14 2.0 s/div 12v 0 a b c d e f 5v 0 12v 0 3.3v 0 a. lx5, 10v/div b. 5v output, 100mv/div c. pwm5 inductor current, 5a/div d. lx3, 10v/div e. 3.3v output, 100mv/div f. pwm3 inductor current, 5a/div linear-regulator startup waveforms max1533/37 toc15 400 s/div 5v 4v 0 a b c d 2v 0 2v 0 2v 0 b. ldo5, 2v/div c. ldo3, 2v/div d. ref, 2v/div 100 ? load on ldo5 and ldo3 a. shdn, 5v/div
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 11 delayed startup waveform (light load) max1533/37 toc16 2ms/div 3.3v 5v 0 a b c d 0 3.3v 0 0 a. on5, 5v/div b. 5v output, 2v/div c. 3.3v ouput, 2v/div d. pgood, 2v/div 100 ? load on out5 and out3, on3 = ref startup waveform (heavy load) max1533/37 toc17 400 s/div 3.3v 0 4v a b c d e 2v 0 2.5a 0 5v 0 a. on5, 5v/div b. 5v output, 2v/div c. inductor current, 5a/div d. ldo5, 1v/div e. dl5, 5v/div 1.0 ? load shutdown waveform (no load) max1533/37 toc18 2ms/div 2v 0 5v a b c d e f 5v 0 0 3.3v 0 5v 0 0 d. 3.3v output, 5v/div e. dl3, 5v/div f. pgood, 5v/div b. 5v output, 5v/div c. dl5, 5v/div a. shdn, 5v/div on3 = on5 = v cc , ovp = gnd shutdown waveform (1 ? load) max1533/37 toc19 100 s/div 2v 0 5v a b c d e 5v 5a 0 5v 0 b. ldo5, 2v/div c. 5v output, 2v/div d. inductor current, 5a/div e. dl5, 5v/div on3 = on5 = v cc , ovp = gnd a. shdn, 5v/div 5v output load transient (forced-pwm) max1533/37 toc20 40 s/div 4a 0 a b c d 5v 4a 0 12v 0 b. v out5 = 5.0v, 100mv/div c. inductor current, 5a/div d. lx5, 10v/div a. i out5 = 0.2a to 4a, 5a/div skip = v cc 3.3v output load transient (forced-pwm) max1533/37 toc21 40 s/div 4a 0 a b c d 3.3v 4a 0 12v 0 b. v out3 = 3.3v, 100mv/div c. inductor current, 5a/div d. lx3, 10v/div a. i out3 = 0.2a to 4a, 5a/div skip = v cc typical operating characteristics (continued) (MAX1537 circuit of figure 1, v in = 12v, ldo5 = v cc = 5v, skip = gnd, fsel = ref, t a = +25?, unless otherwise noted.)
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 12 ______________________________________________________________________________________ 3.3v output load transient (pulse skipping) max1533/37 toc22 40 s/div 4a 0 a b c d 3.3v 4a 0 12v 0 b. v out3 = 3.3v, 100mv/div c. inductor current, 5a/div d. lx3, 10v/div a. i out3 = 0.2a to 4a, 5a/div skip = gnd output overload (uvp enabled) max1533/37 toc23 4 s/div 5v 0 a b c 3.3v 0 7a 12v b. 3.3v output, 3.3v/div c. load (0 to 30a), 20a/div a. pgood2, 5v/div d e 30a 0 0 0 d. inductor current, 10a/div e. lx3, 20v/div ldo5 load transient max1533/37 toc24 20 s/div 5v 0 a b c 100ma 0 5.0v 4.95v b. i ldo5 = 1ma to 100ma, 100ma/div c. ldo5, 50m/div on3 = on5 = gnd a. control signal, 5v/div ldo5 line transient max1533/37 toc25 20 s/div 20v a b 15v 4.95v b. ldo5 output voltage, 50mv/div a. input voltage (v in = 7v to 20v), 5v/div 10v 5.05v 5.00v on3 = on5 = gnd, i ldo5 = 20ma 5v auxiliary linear-regulator load transient max1533/37 toc26 100 s/div 120ma a b 10ma 11.90v b. ina, 1v/div a. i ldoa = 10ma to 100ma, 100ma/div 14v 13v 11.96v c. ldoa, 50mv/div c ina = voltage generated by secondary transformer winding typical operating characteristics (continued) (MAX1537 circuit of figure 1, v in = 12v, ldo5 = v cc = 5v, skip = gnd, fsel = ref, t a = +25?, unless otherwise noted.)
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 13 pin description pin max1533 MAX1537 name function 1 adja auxiliary feedback input. connect a resistive voltage-divider from ldoa to analog ground to adjust the auxiliary linear-regulator output voltage. adja regulates at 2v. connect adja to gnd for nominal 12v output using internal feedback. 1 2 on5 5v smps enable input. the 5v smps is enabled if on5 is greater than the smps on level and disabled if on5 is less than the smps off level. if on5 is connected to ref, the 5v smps starts after the 3.3v smps reaches regulation (delay start). drive on5 below the clear fault level to reset the fault latches. 2 3 on3 3.3v smps enable input. the 3.3v smps is enabled if on3 is greater than the smps on level and disabled if on3 is less than the smps off level. if on3 is connected to ref, the 3.3v smps starts after the 5v smps reaches regulation (delay start). drive on3 below the clear fault level to reset the fault latches. 4 ona ldoa enable input. when ona is low, ldoa is high impedance and the secondary winding control is off. when ona is high, ldoa is on. connect to ldo3, ldo5, csl3, csl5, or other output for desired automatic startup sequencing. 3 5 fsel frequency-select input. this three-level logic input sets the controller? switching frequency. connect to gnd, ref, or v cc to select the following typical switching frequencies: v cc = 500khz, ref = 300khz, gnd = 200khz 4 6 ilim3 3.3v smps peak current-limit threshold adjustment. the current-limit threshold defaults to 75mv if ilim3 is connected to v cc . in adjustable mode, the current-limit threshold across csh3 and csl3 is precisely 1/10th the voltage seen at ilim3 over a 500mv to 2.0v range. the logic threshold for switchover to the 75mv default value is approximately v cc - 1v. 5 7 ilim5 5v s m p s p eak c ur r ent- li m i t thr eshol d . the cur r ent- l i m i t thr eshol d d efaul ts to 75m v i f ilim 5 i s connected to v c c . in ad j ustab l e m od e, the cur r ent- l i m i t thr eshol d acr oss c s h 5 and c s l5 i s p r eci sel y 1/10th the vol tag e seen at ilim 5 over a 500m v to 2.0v r ang e. the l og i c thr eshol d for sw i tchover to the 75m v d efaul t val ue i s ap p r oxi m atel y v c c - 1v . 6 8 ref 2.0v reference voltage output. bypass ref to analog ground with a 0.1? or greater ceramic capacitor. the reference can source up to 100? for external loads. loading ref degrades output-voltage accuracy according to the ref load-regulation error. the reference shuts down when shdn is low. 7 9 gnd analog ground. connect the backside pad to gnd. 810 v cc analog supply input. connect to the system supply voltage (+4.5v to +5.5v) through a series 20 ? resistor. bypass v cc to analog ground with a 1? or greater ceramic capacitor. 9 11 pgdly power-good one-shot delay. place a timing capacitor on pgdly to delay pgood going high. pgdly has a 5? pullup current and a 10 ? pulldown. the pulldown is activated when power is not good. when power is good, the pulldown is shut off and the 5? pullup is activated. when pgdly crosses ref, pgood is enabled.
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 14 ______________________________________________________________________________________ pin description (continued) pin max1533 MAX1537 name function 10 12 pgood open-drain power-good output. pgood is low if either output is more than 10% (typ) below the normal regulation point, during soft-start, and in shutdown. pgood is delayed on the rising edge by the pgdly one-shot timer. pgood becomes high impedance when both smps outputs are in regulation. 11 13 uvp undervoltage fault-protection control. connect uvp to gnd to select the default overvoltage threshold of 70% of nominal. connect to v cc to disable undervoltage protection and clear the undervoltage fault latch. 12 14 dh3 high-side gate-driver output for 3.3v smps. dh3 swings from lx3 to bst3. 13 15 bst3 boost flying-capacitor connection for 3.3v smps. connect to an external capacitor and diode as shown in figure 6. an optional resistor in series with bst3 allows the dh3 pullup current to be adjusted. 14 16 lx3 inductor connection for 3.3v smps. connect lx3 to the switched side of the inductor. lx3 serves as the lower supply rail for the dh3 high-side gate driver. 15 17 ovp overvoltage fault-protection control. connect ovp to gnd to select the default overvoltage threshold of +11% above nominal. connect to v cc to disable overvoltage protection and clear the overvoltage fault latch. 16 18 csh3 positive current-sense input for 3.3v smps. connect to the positive terminal of the current-sense element. figure 9 describes two different current-sensing options. 17 19 csl3 negative current-sense input for 3.3v smps. connect to the negative terminal of the current-sense element. figure 9 describes two different current-sensing options. csl3 also serves as the bootstrap input for ldo3. 18 20 fb3 feedback input for 3.3v smps. connect to gnd for fixed 3.3v output. in adjustable mode, fb3 regulates to 1v. 19 21 ldo3 3.3v internal linear-regulator output. bypass with 2.2? (min) (1?/20ma). provides 100ma (min). power is taken from ldo5. if csl3 is greater than 3v, the linear regulator shuts down and ldo3 connects to csl3 through a 1 ? switch rated for loads up to 200ma. 20 22 dl3 low-side gate-driver output for 3.3v smps. dl3 swings from pgnd to ldo5. 21 23 pgnd power ground 22 24 dl5 low-side gate-driver output for 5v smps. dl5 swings from pgnd to ldo5. 23 25 ldo5 5v internal linear-regulator output. bypass with 2.2? (min) (1?/20ma). provides power for the dl_ low-side gate drivers, the dh_ high-side drivers through the bst diodes, the pwm controller, logic, and reference through the v cc pin, as well as the ldo3 internal 3.3v linear regulator. provides 100ma (min) for external loads (+25ma for gate drivers). if csl5 is greater than 4.5v, the linear regulator shuts down and ldo5 connects to csl5 through a 0.75 ? switch rated for loads up to 200ma. 24 26 fb5 feedback input for 5v smps. connect to gnd for fixed 5v output. in adjustable mode, fb5 regulates to 1v.
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 15 pin description (continued) pin max1533 MAX1537 name function 25 27 csl5 negative current-sense input for 5v smps. connect to the negative terminal of the current-sense element. figure 9 describes two different current-sensing options. csl5 also serves as the bootstrap input for ldo5. 26 28 csh5 positive current-sense input for 5v smps. connect to the positive terminal of the current-sense element. figure 9 describes two different current-sensing options. 27 29 in input of the startup circuitry and the ldo5 internal 5v linear regulator. bypass to pgnd with 0.22? close to the ic. 28 30 lx5 inductor connection for 5v smps. connect lx5 to the switched side of the inductor. lx5 serves as the lower supply rail for the dh5 high-side gate driver. 29 31 bst5 boost flying-capacitor connection for 5v smps. connect to an external capacitor and diode as shown in figure 6. an optional resistor in series with bst5 allows the dh5 pullup current to be adjusted. 30 32 dh5 high-side gate-driver output for 5v smps. dh5 swings from lx5 to bst5. 31 33 skip pulse-skipping control input. connect to v cc for low-noise forced-pwm mode. connect to gnd for high-efficiency pulse-skipping mode at light loads. 32 34 shdn shutdown control input. the device enters its 5? supply-current shutdown mode if v shdn is less than the shdn input falling-edge trip level and does not restart until v shdn is greater than the shdn input rising-edge trip level. connect shdn to v in for automatic startup. shdn can be connected to v in through a resistive voltage-divider to implement a programmable undervoltage lockout. 35 ina supply voltage input for the auxiliary ldoa linear regulator. ina is clamped with an internal shunt to 26v. 36 ldoa adjustable (12v nominal) 150ma auxiliary linear-regulator output. input supply comes from ina. bypass ldoa to gnd with 2.2? (min) (1?/20ma). secondary feedback threshold is set at ina - ldoa = 0.8v, and triggers the dl5 on the 5v smps only. ona high enables regulator output and secondary regulation. pgood is not affected by the state of ldoa.
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 16 ______________________________________________________________________________________ component 5a/300khz 5a/500khz input voltage v in = 7v to 24v v in = 7v to 24v c in_ , input capacitor (2) 10?, 25v taiyo yuden tmk432bj106km (2) 10?, 25v taiyo yuden tmk432bj106km c out5 , output capacitor 150?, 6.3v, 40m ? , low-esr capacitor sanyo 6tpb150ml 150?, 6.3v, 40m ? , low-esr capacitor sanyo 6tpb150ml c out3 , output capacitor 220?, 4v, 40m ? , low-esr capacitor sanyo 4tpb220ml 220?, 4v, 40m ? , low-esr capacitor sanyo 4tpb220ml n h_ high-side mosfet fairchild semiconductor fds6612a international rectifier irf7807v fairchild semiconductor fds6612a international rectifier irf7807v n l_ low-side mosfet fairchild semiconductor fds6670s international rectifier irf7807vd1 fairchild semiconductor fds6670s international rectifier irf7807vd1 d l_ schottky rectifier (if needed) 2a, 30v, 0.45v f nihon ec21qs03l 2a, 30v, 0.45v f nihon ec21qs03l inductor/transformer t1 = 6.8?, 1:2 turns sumida 4749-t132 l1 = 5.8?, 8.6a sumida cdrh127-5r8nc 3.9? sumida cdrh124-3r9nc r cs 10m ? 1%, 0.5w resistor irc lr2010-01-r010f or dale wsl-2010-r010f 10m ? 1%, 0.5w resistor irc lr2010-01-r010f or dale wsl-2010-r010f supplier website avx www.avx.com central semiconductor www.centralsemi.com coilcraft www.coilcraft.com coiltronics www.coiltronics.com fairchild semiconductor www.fairchildsemi.com international rectifier www.irf.com kemet www.kemet.com detailed description the max1533/MAX1537 standard application circuit (figure 1) generates the 5v/5a and 3.3v/5a typical of the main supplies in a notebook computer. the input supply range is 7v to 24v. see table 1 for component selections and table 2 for component manufacturers. the max1533/MAX1537 contain two interleaved fixed- frequency step-down controllers designed for low- voltage power supplies. the optimal interleaved archi- tecture guarantees out-of-phase operation, reducing the input capacitor ripple. two internal ldos generate the keep-alive 5v and 3.3v power. the MAX1537 has an auxiliary ldo that can be configured to the preset 12v output or an adjustable output. fixed linear regulators (ldo5 and ldo3) two internal linear regulators produce preset 5v (ldo5) and 3.3v (ldo3) low-power outputs. ldo5 powers ldo3, the gate drivers for the external mosfets, and provides the bias supply (v cc ) required for the smps analog control, reference, and logic blocks. ldo5 supplies at least 100ma for external and internal loads, including the mosfet gate drive, which typically varies from 5ma to 50ma, depending on the switching frequen- cy and external mosfets selected. ldo3 also supplies at least 100ma for external loads. bypass ldo5 and ldo3 with a 2.2? or greater output capacitor, using an additional 1.0? per 20ma of internal and external load. table 1. component selection for standard applications table 2. component suppliers supplier website panasonic www.panasonic.com/industrial sanyo www.secc.co.jp sumida www.sumida.com taiyo yuden www.t-yuden.com tdk www.component.tdk.com toko www.tokoam.com vishay (dale, siliconix) www.vishay.com
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 17 figure 1. max1533/MAX1537 standard application circuit r3 60.4k ? r4 100k ? r5 60.4k ? ldo5 dh3 bst3 dl3 lx3 csh3 ilim5 c bst 0.1 f n h2 d l2 r cs2 10m ? c out2 150 f 40m ? ref (300khz) connect to ldo5 power-good 3.3v ldo output n l2 c bst 0.1 f n h1 n l1 r cs1 10m ? c out1 220 f 40m ? d l1 l1 5.8 h d bst d bst c1 10 f 5v ldo output 3.3v pwm output c ref 0.22 f input (v in ) see table 1 for component specifications shdn fb3 ovp power ground analog ground max1533 MAX1537 ref c in (2) 10 f on off 12v ldo output MAX1537 only on3 on5 ina ona r2 100k ? bst5 lx5 dl5 pgnd gnd csh5 csl5 fb5 uvp skip dh5 in ilim3 csl3 on off secondary output on off c5 22 f d1 5v pwm output secondary output t1 1:2 turns lp = 6.8 h fsel vcc pgood pgdly r1 20 ? c2 1 f r8 100k ? ldo3 c3 10 f r7 0 ? c4 10 f ldoa adja r6 open
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 18 ______________________________________________________________________________________ smps to ldo bootstrap switchover when the 5v main output voltage is above the ldo5 bootstrap-switchover threshold, an internal 0.75 ? (typ) p-channel mosfet shorts csl5 to ldo5 while simulta- neously shutting down the ldo5 linear regulator. similarly, when the 3.3v main output voltage is above the ldo3 bootstrap-switchover threshold, an internal 1 ? (typ) p-channel mosfet shorts csl3 to ldo3 while simultaneously shutting down the ldo3 linear regula- tor. these actions bootstrap the device, powering the internal circuitry and external loads from the output smps voltages, rather than through linear regulators from the battery. bootstrapping reduces power dissipa- tion due to gate charge and quiescent losses by pro- viding power from a 90%-efficient switch-mode source, rather than from a much-less-efficient linear regulator. the output current limit increases to 200ma when the ldo_ outputs are switched over. smps 5v bias supply (ldo5 and v cc ) the a switch-mode power supplies (smps) require a 5v bias supply in addition to the high-power input sup- ply (battery or ac adapter). this 5v bias supply is gen- erated by the max1533/MAX1537s?internal 5v linear regulator (ldo5). this bootstrapped ldo allows the max1533/MAX1537 to power-up independently. the gate-driver input supply is connected to the fixed 5v linear-regulator output (ldo5). therefore, the 5v ldo supply must provide v cc (pwm controller) and the gate-drive power, so the maximum supply current required is: i bias = i cc + f sw (q g(low) + q g(high) ) = 5ma to 50ma (typ) where i cc is 1ma (typ), f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheet? total gate-charge specification limits at v gs = 5v. reference (ref) the 2v reference is accurate to ?% over temperature and load, making ref useful as a precision system ref- erence. bypass ref to gnd with a 0.22? or greater ceramic capacitor. the reference sources up to 100? and sinks 10? to support external loads. if highly accurate specifications ( 0.5%) are required for the main smps output voltages, the reference should not be loaded. loading the reference reduces the ldo5, ldo3, out5, and out3 output voltages slightly because of the reference load-regulation error. system enable/shutdown ( shdn ) drive shdn below the precise shdn input falling-edge trip level to place the max1533/MAX1537 in their low- power shutdown state. the max1533/MAX1537 con- sume only 5? of quiescent current while in shutdown mode. when shutdown mode activates, the reference turns off, making the threshold to exit shutdown less accurate. to guarantee startup, drive shdn above 2.2v ( shdn input rising-edge trip level). for automatic shutdown and startup, connect shdn to v in . the accu- rate 1v falling-edge threshold on shdn can be used to detect a specific input-voltage level and shut the device down. once in shutdown, the 1.6v rising-edge threshold activates, providing sufficient hysteresis for most applications. smps detailed description smps por, uvlo, and soft-start power-on reset (por) occurs when v cc rises above approximately 1v, resetting the undervoltage, overvolt- age, and thermal-shutdown fault latches. the por cir- cuit also ensures that the low-side drivers are pulled low if ovp is disabled ( ovp = v cc ), or driven high if ovp is enabled ( ovp = gnd) until the smps con- trollers are activated. the v cc input undervoltage-lockout (uvlo) circuitry inhibits switching if the 5v bias supply (ldo5) is below the 4v input uvlo threshold. once the 5v bias supply (ldo5) rises above this input uvlo threshold and the controllers are enabled, the smps controllers start switching and the output voltages begin to ramp up using soft-start. the internal digital soft-start gradually increases the internal current-limit level during startup to reduce the input surge currents. the max1533/MAX1537 divide the soft-start period into five phases. during the first phase, each controller limits its current limit to only 20% of its full current limit. if the output does not reach regulation within 128 clock cycles (1 / f osc ), soft-start enters the second phase and the current limit is increased by another 20%. this process repeats until the maximum current limit is reached after 512 clock cycles (1 / f osc ) or when the output reaches the nominal regulation volt- age, whichever occurs first (see the startup waveforms in the typical operating characteristics ).
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 19 figure 2. max1533/MAX1537 functional diagram v cc ref r r fb3 2.0v ref dh5 bst5 lx5 ldo5 dl5 pwm5 controller (figure 3) dh3 bst3 dl3 ldo5 lx3 pwm3 controller (figure 3) pgnd fb decode (figure 5) on3 in fsel fb decode (figure 5) fb5 on5 ilim5 csh5 csl5 ilim3 csh3 csl3 ovp pgood power-good and fault protection (figure 7) internal fb fault adja ldoa ina ona skip uvp 5v linear regulator 3.3v linear regulator ldo5 pgdly MAX1537 auxiliary linear regulator (figure 8) gnd ldo3 ldo bypass circuitry ldo bypass circuitry osc shdn secondary feedback max1533/MAX1537
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 20 ______________________________________________________________________________________ smps enable controls (on3, on5) on3 and on5 control smps power-up sequencing. on3 or on5 rising above 2.4v enables the respective outputs. on3 or on5 falling below 1.6v disables the respective outputs. driving on_ below 0.8v clears the overvoltage, undervoltage, and thermal fault latches. smps power-up sequencing connecting on3 or on5 to ref forces the respective outputs off while the other output is below regulation and starts after that output regulates. the second smps remains on until the first smps turns off, the device shuts down, a fault occurs, or ldo5 goes into undervolt- age lockout. both supplies begin their power-down sequence immediately when the first supply turns off. output discharge (soft-shutdown) when output discharge is enabled ( ovp pulled low) and the switching regulators are disabled?y transi- tions into standby or shutdown mode, or when an output undervoltage fault occurs?he controller dis- charges both outputs through internal 12 ? switches, until the output voltages decrease to 0.3v. this slowly discharges the output capacitance, providing a soft- damped shutdown response. this eliminates the slight- ly negative output voltages caused by quickly discharging the output through the inductor and low- side mosfet. when an smps output discharges to 0.3v, its low-side driver (dl_) is forced high, clamping the respective smps output to gnd. the reference remains active to provide an accurate threshold and to provide overvoltage protection. both smps controllers contain separate soft-shutdown circuits. when output discharge is disabled ( ovp = v cc ), the low- side drivers (dl_) and high-side drivers (dh_) are both pulled low, forcing lx into a high-impedance state. since the outputs are not actively discharged by the smps con- trollers, the output-voltage discharge rate is determined only by the output capacitance and load current. fixed-frequency, current-mode pwm controller the heart of each current-mode pwm controller is a multi- input, open-loop comparator that sums two signals: the output-voltage error signal with respect to the reference voltage and the slope-compensation ramp (figure 3). the max1533/MAX1537 use a direct-summing configu- ration, approaching ideal cycle-to-cycle control over the output voltage without a traditional error amplifier and the phase shift associated with it. the max1533/MAX1537 use a relatively low loop gain, allowing the use of low- cost output capacitors. the low loop gain results in the -0.1% typical load-regulation error and helps reduce the output capacitor size and cost by shifting the unity- gain crossover frequency to a lower level. table 3. operating modes inputs* outputs mode shdn on5 on3 ldo5 ldo3 5v smps 3v smps shutdown mode low x x off off off off standby mode high low low on on off off normal operation high high high on on on on 3.3v smps active high low high on on off on 5v smps active high high low on on on off normal operation (delayed 5v smps startup) high ref high on on on power-up after 3.3v smps is in regulation on normal operation (delayed 3.3v smps startup) high high ref on on on on power-up after 5v smps is in regulation * shdn is an accurate, low-voltage logic input with 1v falling-edge threshold voltage and 1.6v rising-edge threshold voltage. on3 and on5 are 3-level cmos logic inputs, a logic-low voltage is less than 0.8v, a logic-high voltage is greater than 2.4v, and th e mid- dle logic level is between 1.9v and 2.1v (see the electrical characteristics table).
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 21 figure 3: pwm-controller functional diagram s r q r s q dh driver dl driver slope comp dac counter soft-start current limit on osc from fb ref / 2 csl csh idle- mode current 0.2 x v limit secondary feedback 0.8v one-shot -1.2 x v limit lx pgnd MAX1537 only agnd (see figure 5) skip
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 22 ______________________________________________________________________________________ frequency selection (fsel) the fsel input selects the pwm-mode switching fre- quency. table 4 shows the switching frequency based on fsel connection. high-frequency (500khz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra-portable devices where the load currents are lower. low-frequency (200khz) operation offers the best overall efficiency at the expense of component size and board space. forced-pwm mode the low-noise forced-pwm mode disables the zero- crossing comparator, which controls the low-side switch on-time. this forces the low-side gate-drive waveform to constantly be the complement of the high-side gate- drive waveform, so the inductor current reverses at light loads while dh_ maintains a duty factor of v out / v in . the benefit of forced-pwm mode is to keep the switch- ing frequency fairly constant. however, forced-pwm operation comes at a cost: the no-load 5v supply current remains between 15ma and 50ma, depending on the external mosfets and switching frequency. forced-pwm mode is most useful for avoiding audio- frequency noise and improving load-transient response. since forced-pwm operation disables the zero-crossing comparator, the inductor current revers- es under light loads. light-load operation control ( skip ) the max1533/MAX1537 include a light-load operating- mode control input ( skip ) used to independently enable or disable the zero-crossing comparator for both controllers. when the zero-crossing comparator is enabled, the controller forces dl_ low when the cur- rent-sense inputs detect zero inductor current. this keeps the inductor from discharging the output capaci- tors and forces the controller to skip pulses under light- load conditions to avoid overcharging the output. when the zero-crossing comparator is disabled, the controller is forced to maintain pwm operation under light-load conditions (forced-pwm). idle-mode current-sense threshold the on-time of the step-down controller terminates when the output voltage exceeds the feedback thresh- old and when the current-sense voltage exceeds the idle-mode current-sense threshold. under light-load conditions, the on-time duration depends solely on the idle-mode current-sense threshold, which is approxi- mately 20% of the full-load current-limit threshold set by ilim_. this forces the controller to source a minimum amount of power with each cycle. to avoid overcharg- ing the output, another on-time cannot begin until the output voltage drops below the feedback threshold. since the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses. therefore, the controller regulates the valley of the output ripple under light-load conditions. automatic pulse-skipping crossover in skip mode, an inherent automatic switchover to pfm takes place at light loads (figure 4). this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current? zero crossing. the zero-crossing comparator senses the inductor cur- rent across the low-side mosfet (pgnd to lx_). once v pgnd - v lx _ drops below the 3mv zero-crossing cur- rent-sense threshold, the comparator forces dl_ low (figure 3). this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between con- tinuous and discontinuous inductor-current operation (also known as the ?ritical conduction?point). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is given by: the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input-voltage levels). i vvv vf l load skip out in out in sw () ( ) = ? 2 table 4. fsel configuration table fsel switching frequency v cc 500khz ref 300khz gnd 200khz
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 23 output voltage dc output accuracy specifications in the electrical characteristics table refer to the error-comparator? threshold. when the inductor continuously conducts, the max1533/MAX1537 regulate the peak of the output ripple, so the actual dc output voltage is lower than the slope-compensated trip level by 50% of the output rip- ple voltage. for pwm operation (continuous conduc- tion), the output voltage is accurately defined by the following equation: where v nom is the nominal output voltage, a slope equals 1%, and v ripple is the output ripple voltage (v ripple = esr x ? i inductor as described in the output capacitor selection section). in discontinuous conduction (i out < i load(skip) ), the max1533/MAX1537 regulate the valley of the output ripple, so the output voltage has a dc regulation level higher than the error-comparator threshold. for pfm operation (discontinuous conduction), the output volt- age is approximately defined by the following equation: where v nom is the nominal output voltage, f osc is the maximum switching frequency set by the internal oscil- lator, f sw is the actual switching frequency, and i idle is the idle-mode inductor current when pulse skipping. adjustable/fixed output voltages (dual-mode feedback) connect fb3 and fb5 to gnd to enable the fixed smps output voltages (3.3v and 5v, respectively), set by a preset, internal resistive voltage-divider connected between csl_ and analog ground. connect a resistive voltage-divider at fb_ between csl_ and gnd to adjust the respective output voltage between 1v and 5.5v (figure 5). choose r2 (resistance from fb to gnd) to be about 10k ? and solve for r1 (resistance from out to fb) using the equation: where v fb_ = 1v nominal. rr v v out fb 12 1 _ _ = ? ? ? ? ? ? ? vv f f i esr out pfm nom sw osc idle () =+ ? ? ? ? ? ? 1 2 vv av v v out pwm nom slope nom in ripple () = ? ? ? ? ? ? ? ? ? ? ? ? 1 2 - - t on(skip) i idle l v in - v out inductor current i load(skip) time on-time 0 csl to error amplifier ref (2.0v) r 12r fb fixed output fb = gnd adjustable output figure 4. pulse-skipping/discontinuous crossover point figure 5. dual-mode feedback decoder
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 24 ______________________________________________________________________________________ when adjusting both output voltages, set the 3.3v smps lower than the 5v smps. ldo5 connects to the 5v output (csl5) through an internal switch only when csl5 is above the ldo5 bootstrap threshold (4.56v). similarly, ldo3 connects to the 3.3v output (csl3) through an internal switch only when csl3 is above the ldo3 bootstrap threshold (2.91v). bootstrapping works most effectively when the fixed output voltages are used. once ldo_ is bootstrapped from csl_, the inter- nal linear regulator turns off. this reduces internal power dissipation and improves efficiency at higher input voltage. current-limit protection (ilim_) the current-limit circuit uses differential current-sense inputs (csh_ and csl_) to limit the peak inductor cur- rent. if the magnitude of the current-sense signal exceeds the current-limit threshold, the pwm controller turns off the high-side mosfet (figure 3). at the next rising edge of the internal oscillator, the pwm controller does not initiate a new cycle unless the current-sense signal drops below the current-limit threshold. the actual maximum load current is less than the peak cur- rent-limit threshold by an amount equal to half of the inductor ripple current. therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (v out / v in ). in forced-pwm mode, the max1533/MAX1537 also implement a negative current limit to prevent excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approxi- mately 120% of the positive current limit and tracks the positive current limit when ilim_ is adjusted. connect ilim_ to v cc for the 75mv default threshold, or adjust the current-limit threshold with an external resis- tor-divider at ilim_. use a 2? to 20? divider current for accuracy and noise immunity. the current-limit threshold adjustment range is from 50mv to 200mv. in the adjustable mode, the current-limit threshold voltage equals precisely 1/10th the voltage seen at ilim_. the logic threshold for switchover to the 75mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the dif- ferential current-sense signals seen by csh_ and csl_. place the ic close to the sense resistor with short, direct traces, making a kelvin-sense connection to the current-sense resistor. mosfet gate drivers (dh_, dl_) the dh_ and dl_ drivers are optimized for driving moderate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differential exists. the high-side gate drivers (dh_) source and sink 2a, and the low-side gate dri- vers (dl_) source 1.7a and sink 3.3a. this ensures robust gate drive for high-current applications. the dh_ floating high-side mosfet drivers are powered by diode-capacitor charge pumps at bst_ (figure 6) while the dl_ synchronous-rectifier drivers are powered directly by the fixed 5v linear regulator (ldo5). adaptive dead-time circuits monitor the dl_ and dh_ drivers and prevent either fet from turning on until the other is fully off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from the dl_ and dh_ drivers to the mosfet gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the max1533/ MAX1537 interprets the mosfet gates as ?ff?while charge actually remains. use very short, wide traces (50 to 100 mils wide if the mosfet is 1 inch from the driver). the internal pulldown transistor that drives dl_ low is robust, with a 0.6 ? (typ) on-resistance. this helps pre- vent dl_ from being pulled up due to capacitive cou- pling from the drain to the gate of the low-side mosfets when the inductor node (lx_) quickly switch- es from ground to v in . applications with high input volt- ages and long inductive driver traces may require additional gate-to-source capacitance to ensure fast- rising lx_ edges do not pull up the low-side mosfets gate, causing shoot-through currents. the capacitive coupling between lx_ and dl_ created by the mosfet? gate-to-drain capacitance (c rss ), gate-to- source capacitance (c iss - c rss ), and additional board parasitics should not exceed the following minimum threshold: lot-to-lot variation of the threshold voltage may cause problems in marginal designs. alternatively, adding a resistor less than 10 ? in series with bst_ may remedy the problem by increasing the turn-on time of the high- side mosfet without degrading the turn-off time (figure 6). vv c c gs th in rss iss () > ? ? ? ? ? ?
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 25 power-good output (pgood) pgood is the open-drain output of a comparator that continuously monitors both smps output voltages for undervoltage conditions. pgood is actively held low in shutdown ( shdn or on3 or on5 = gnd), soft-start, and soft-shutdown. once the digital soft-start termi- nates, pgood becomes high impedance as long as both outputs are above 90% of the nominal regulation voltage set by fb_. pgood goes low once either smps output drops 10% below its nominal regulation point, an output overvoltage fault occurs, or either smps controller is shut down. for a logic-level pgood output voltage, connect an external pullup resistor between pgood and v cc . a 100k ? pullup resistor works well in most applications. pgood is independent of the fault protection states ovp and uvp . fault protection output overvoltage protection (ovp) if the output voltage of either smps rises above 111% of its nominal regulation voltage and the ovp protection is enabled ( ovp = gnd), the controller sets the fault latch, pulls pgood low, shuts down both smps con- trollers, and immediately pulls dh_ low and forces dl_ max1533 MAX1537 ldo5 bst dh lx (r bst )* (c nl )* d bst c bst c byp input (v in ) n h l ldo5 dl gnd n l (r bst )* optional?he resistor lowers emi by decreasing the switching-node rise time. (c nl )* optional?he capacitor reduces lx to dl capacitive coupling that can cause shoot-through currents. figure 6. optional gate-driver circuitry por enable ovp enable uvp blank (power-up) power- good fault 0.9 x int ref_ 0.7 x int ref_ 1.11 x int ref_ fault latch timer power-good fault protection internal fb figure 7. power-good and fault protection
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 26 ______________________________________________________________________________________ high. this turns on the synchronous-rectifier mosfets with 100% duty, rapidly discharging the output capaci- tors and clamping both outputs to ground. however, immediately latching dl_ high typically causes slightly negative output voltages due to the energy stored in the output lc at the instant the ovp occurs. if the load cannot tolerate a negative voltage, place a power schottky diode across the output to act as a reverse- polarity clamp. if the condition that caused the overvolt- age persists (such as a shorted high-side mosfet), the battery fuse blows. cycle v cc below 1v or toggle either on3, on5, or shdn to clear the fault latch and restart the smps controllers. connect ovp to v cc to disable the output overvoltage protection. output undervoltage protection (uvp) each smps controller includes an output uvp protec- tion circuit that begins to monitor the output 6144 clock cycles (1 / f osc ) after that output is enabled (on_ pulled high). if either smps output voltage drops below 70% of its nominal regulation voltage and the uvp pro- tection is enabled ( uvp = gnd), the uvp circuit sets the fault latch, pulls pgood low, and shuts down both controllers using discharge mode (see the output discharge (soft-shutdown) section). when an smps output voltage drops to 0.3v, its synchronous rectifier turns on, clamping the discharged output to gnd. cycle v cc below 1v or toggle either on3, on5, or shdn to clear the fault latch and restart the smps controllers. connect uvp to v cc to disable the output undervoltage protection. table 5. operating modes truth table mode condition comment power-up ldo5 < uvlo threshold. transitions to discharge mode after v in por and after ref becomes valid. ldo5, ldo3, ref remain active. dl_ is active if ovp is low. run shdn = high, on3 or on5 enabled. normal operation. output overvoltage protection (ovp) either output > 111% of nominal level, ovp = low. exited by por or cycling shdn , on3, or on5. output undervoltage protection (uvp) either output < 70% of nominal level, uvp is enabled 6144 clock cycles (1 / f osc ) after the output is enabled and uvp = low. exited by por or cycling shdn , on3, or on5. if ovp is not high, dl3 and dl5 go high after discharge. discharge ovp is low and either smps output is still high in either standby mode or shutdown mode. discharge switch (10 ? ) connects csl_ to pgnd. this is a temporary state entered when ldo5 is undervoltage or on the way to output uvlo, standby, shutdown, or thermal-shutdown states. one smps can be in discharge mode while the other is in run mode. if both outputs are discharged to 0.3v (on csl_), discharge mode transitions to the appropriate state. standby on5 and on3 < startup threshold, shdn = high. dl_ stays high if ovp is low. ldo3, ldo5 active. shutdown shdn = low. all circuitry off. thermal shutdown t j > +160?. exited by por or cycling shdn , on3, or on5. if ovp is not high, dl3 and dl5 go high before ldo5 turns off. switchover fault excessive current on ldo3 or ldo5 switchover transistors. exited by por or cycling shdn , on3, or on5. if ovp is not high, dl3 and dl5 go high before ldo5 turns off.
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 27 thermal fault protection the max1533/MAX1537 feature a thermal fault-protec- tion circuit. when the junction temperature rises above +160 c, a thermal sensor activates the fault latch, pulls pgood low, and shuts down both smps controllers using discharge mode (see the output discharge (soft- shutdown) section). when an smps output voltage drops to 0.3v, its synchronous rectifier turns on, clamp- ing the discharged output to gnd. cycle v cc below 1v or toggle either on3, on5, or shdn to clear the fault latch and restart the controllers after the junction tem- perature cools by 15 c. auxiliary ldo detailed description (MAX1537 only) the MAX1537 includes an auxiliary linear regulator that delivers up to 150ma of load current. the output (ldoa) can be preset to 12v, ideal for pcmcia power requirements, and for biasing the gates of load switch- es in a portable device. in adjustable mode, ldoa can be set to anywhere from 5v to 23v. the auxiliary regu- lator has an independent on/off control, allowing it to be shut down when not needed, reducing power con- sumption when the system is in a low-power state. a flyback-winding control loop regulates a secondary winding output, improving cross-regulation when the pri- mary output is lightly loaded or when there is a low input-output differential voltage. if v ina - v ldoa falls below 0.8v, the low-side switch is turned on for a time equal to 33% of the switching period. this reverses the inductor (primary) current, pulling current from the out- put filter capacitor and causing the flyback transformer to operate in forward mode. the low impedance pre- sented by the transformer secondary in forward mode dumps current into the secondary output, charging up the secondary capacitor and bringing v ina - v ldoa back into regulation. the secondary feedback loop does not improve secondary output accuracy in normal fly- back mode, where the main (primary) output is heavily loaded. in this condition, secondary output accuracy is determined by the secondary rectifier drop, transformer turns ratio, and accuracy of the main output voltage. adjustable ldoa voltage (dual-mode feedback) connect adja to gnd to enable the fixed, preset 12v auxiliary output. connect a resistive voltage-divider at adja between ldoa and gnd to adjust the respective output voltage between 5v and 23v (figure 8). choose r2 (resistance from adja to gnd) to be approximately 100k ? and solve for r1 (resistance from ldoa to adja) using the following equation: where v adja = 2v nominal. design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range. the maximum value (v in(max) ) must accommodate the worst-case, high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to connectors, fuses, and battery-selector switches. if there is a choice at all, lower input volt- ages result in better efficiency. rr v v ldoa adja 12 1 = ? ? ? ? ? ? - figure 8. linear-regulator functional diagram fixed 12v ina adja ldoa ona 0.15v secondary feedback ref (2.0v) 5r r
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 28 ______________________________________________________________________________________ maximum load current. there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil- tering requirements and thus drives output-capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load cur- rent (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing com- ponents. switching frequency. this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target, due to rapid improvements in mosfet technology that are mak- ing higher frequencies more practical. inductor operating point. this choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc- tion (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction bene- fit. the optimum operating point is usually found between 20% and 50% ripple current. when pulse skipping ( skip low and light loads), the inductor value also determines the load-current value at which pfm/pwm switchover occurs. inductor selection the switching frequency and inductor operating point determine the inductor value as follows: for example: i load(max) = 5a, v in = 12v, v out = 5v, f osc = 300khz, 30% ripple current or lir = 0.3. find a low-loss inductor with the lowest possible dc resistance that fits in the allotted dimensions. most inductor manufacturers provide inductors in standard values, such as 1.0?, 1.5?, 2.2?, 3.3?, etc. also look for nonstandard values, which can provide a better compromise in lir across the input voltage range. if using a swinging inductor (where the no-load induc- tance decreases linearly with increasing current), evalu- ate the lir with properly scaled inductance values. for the selected inductance value, the actual peak-to-peak inductor ripple current ( ? i inductor ) is defined by: ferrite cores are often the best choice, although pow- dered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): transformer design (for the MAX1537 auxiliary output) a coupled inductor or transformer can be substituted for the inductor in the 5v smps to create an auxiliary output (figure 1). the MAX1537 is particularly well suit- ed for such applications because the secondary feed- back threshold automatically triggers dl5 even if the 5v output is lightly loaded. the power requirements of the auxiliary supply must be considered in the design of the main output. the trans- former must be designed to deliver the required current in both the primary and the secondary outputs with the proper turns ratio and inductance. the power ratings of the synchronous-rectifier mosfets and the current limit in the MAX1537 must also be adjusted according- ly. extremes of low input-output differentials, widely dif- ferent output loading levels, and high turns ratios can further complicate the design due to parasitic trans- former parameters such as interwinding capacitance, secondary resistance, and leakage inductance. power from the main and secondary outputs is combined to get an equivalent current referred to the main output. use this total current to determine the current limit (see the setting the current limit section): i total = p total / v out5 where i total is the equivalent output current referred to the main output, and p total is the sum of the output power from both the main output and the secondary output: ii i peak load max inductor =+ () ? 2 ? i vvv vf l inductor out in out in osc = () - l vv a h . . = () = 512 503 650 -5v 12v 300khz l vv out in = () - v v f i lir out in osc load(max)
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 29 where l primary is the primary inductance, n is the transformer turns ratio, v sec is the minimum required rectified secondary voltage, v fwd is the forward drop across the secondary rectifier, v out5(min) is the mini- mum value of the main output voltage, and v rect is the on-state voltage drop across the synchronous-rectifier mosfet. the transformer secondary return is often con- nected to the main output voltage instead of ground to reduce the necessary turns ratio. in this case, subtract v out5 from the secondary voltage (v sec - v out5 ) in the transformer turns-ratio equation above. the secondary diode in coupled-inductor applications must withstand flyback voltages greater than 60v. common silicon recti- fiers, such as the 1n4001, are also prohibited because they are too slow. fast silicon rectifiers such as the murs120 are the only choice. the flyback voltage across the rectifier is related to the v in - v out difference, according to the transformer turns ratio: v flyback = v sec + (v in - v out5 ) x n where n is the transformer turns ratio (secondary wind- ings/primary windings), and v sec is the maximum sec- ondary dc output voltage. if the secondary winding is returned to v out5 instead of ground, subtract v out5 from v flyback in the equation above. the diode? reverse-breakdown voltage rating must also accommo- date any ringing due to leakage inductance. the diode? current rating should be at least twice the dc load current on the secondary output. transient response the inductor ripple current also impacts transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the total output voltage sag is the sum of the voltage sag while the inductor is ramping up, and the voltage sag before the next pulse can occur. where d max is the maximum duty factor (see the electrical characteristics table), t is the switching period (1 / f osc ), and ? t equals v out / v in x t when in pwm mode, or l x 0.2 x i max / (v in - v out ) when in skip mode. the amount of overshoot during a full-load to no- load transient due to stored inductor energy can be calculated as: setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the peak inductor current occurs at i load(max) plus half the ripple current; therefore: where i limit equals the minimum current-limit threshold voltage divided by the current-sense resistance (r sense ). for the default setting, the minimum current- limit threshold is 70mv. connect ilim_ to v cc for the default current-limit threshold. in adjustable mode, the current-limit thresh- old is precisely 1/10th the voltage seen at ilim_. for an adjustable threshold, connect a resistive divider from ref to analog ground (gnd) with ilim_ connected to the center tap. the external 500mv to 2v adjustment range corresponds to a 50mv to 200mv current-limit threshold. when adjusting the current limit, use 1% tol- erance resistors and a divider current of approximately 10? to prevent significant inaccuracy in the current- limit tolerance. the current-sense method (figure 9) and magnitude determine the achievable current-limit accuracy and power loss. typically, higher current-sense limits pro- vide tighter accuracy, but also dissipate more power. most applications employ a current-limit threshold (v limit ) of 50mv to 100mv, so the sense resistor can be determined by: r sense = v limit / i lim for the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in figure 9a. this configuration constantly monitors the inductor current, allowing accurate current-limit protection. ii i limit load max inductor >+ ? ? ? ? ? ? () ? 2 v il cv soar load max out out = () () ? 2 2 v li cvd v itt c sag load max out in max out load max out = () () + () () () ? ?? 2 2 - - n vv vvv sec fwd out rect sense = + ++ 5
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 30 ______________________________________________________________________________________ alternatively, high-power applications that do not require highly accurate current-limit protection may reduce the overall power dissipation by connecting a series rc circuit across the inductor (figure 9b) with an equivalent time constant: where r l is the inductor? series dc resistance. in this configuration, the current-sense resistance equals the inductor? dc resistance (r sense = r l ). use the worst- case inductance and r l values provided by the induc- tor manufacturer, adding some margin for the induc- tance drop over temperature and load. output capacitor selection the output filter capacitor must have low enough equiv- alent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. the output capaci- tance must be high enough to absorb the inductor energy while transitioning from full-load to no-load con- ditions without tripping the overvoltage fault protection. when using high-capacitance, low-esr capacitors (see the output-capacitor stability considerations section), l r cr l eq eq = figure 9. current-sense configurations max1533 MAX1537 c out input (v in ) inductor c in b) lossless inductor sensing csl_ csh_ gnd dl_ dh_ lx_ c eq r eq max1533 MAX1537 c out input (v in ) n h n l n h n l l c in d l d l a) output series resistor sensing gnd dl_ dh_ lx_ csl_ csh_ r sense
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 31 the filter capacitor? esr dominates the output voltage ripple. so the output capacitor? size depends on the maximum esr required to meet the output voltage rip- ple (v ripple(p-p) ) specifications: in idle mode, the inductor current becomes discontinu- ous, with peak currents set by the idle-mode current- sense threshold (v idle = 0.2v limit ). in idle mode, the no-load output ripple can be determined as follows: the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, polymers, and other electrolytics). when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the over- shoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equa- tions in the transient response section). however, low- capacity filter capacitors typically have high-esr zeros that may affect the overall stability (see the output- capacitor stability considerations ). output-capacitor stability considerations stability is determined by the value of the esr zero rel- ative to the switching frequency. the boundary of insta- bility is given by the following equation: for a typical 300khz application, the esr zero frequency must be well below 95khz, preferably below 50khz. tantalum and os-con capacitors in widespread use at the time of publication have typical esr zero frequen- cies of 25khz. in the design example used for inductor selection, the esr needed to support 25mv p-p ripple is 25mv / 1.5a = 16.7m ? . one 220?/4v sanyo polymer (tpe) capacitor provides 15m ? (max) esr. this results in a zero at 48khz, well within the bounds of stability. for low-input-voltage applications where the duty cycle exceeds 50% (v out / v in 50%), the output ripple volt- age should not be greater than twice the internal slope- compensation voltage: v ripple 0.02 x v out where v ripple equals ? i inductor x r esr . the worst- case esr limit occurs when v in = 2 x v out , so the above equation can be simplified to provide the follow- ing boundary condition: r esr 0.04 x l x f osc do not put high-value ceramic capacitors directly across the feedback sense point without taking precau- tions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. unstable operation manifests itself in two related but distinctly different ways: short/long pulses or cycle skip- ping resulting in a lower switching frequency. instability occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this ?ools?the error comparator into triggering too early or skipping a cycle. cycle skip- ping is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscilla- tions at the output after line or load steps. such pertur- bations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac-current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. for an out-of-phase regulator, the total rms current in the input capacitor is a function of the load currents, the input currents, the duty cycles, and the amount of over- lap as defined in figure 10. the 40/60 optimal interleaved architecture of the max1533/MAX1537 allows the input voltage to go as low as 8.3v before the duty cycles begin to overlap. f f where f rc esr osc esr esr out = 1 2 v vr r ripple p p idle esr sense () ? = v r i lir ripple p p esr load max () ( ) ? =
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 32 ______________________________________________________________________________________ this offers improved efficiency over a regular 180 out- of-phase architecture where the duty cycles begin to overlap below 10v. figure 10 shows the input-capacitor rms current vs. input voltage for an application that requires 5v/5a and 3.3v/5a. this shows the improve- ment of the 40/60 optimal interleaving over 50/50 inter- leaving and in-phase operation. for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to power-up surge currents typical of sys- tems with a mechanical switch or connector in series with the input. choose a capacitor that has less than 10 c temperature rise at the rms input current for opti- mal reliability and lifetime. power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20v) ac adapters. low-cur- rent applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . ideally, the losses at v in(min) should be roughly equal to the losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher, consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher, consider reducing the size of n h . if v in does not vary over a wide range, maximum efficiency is achieved by selecting a high-side mosfet (n h ) that has conduction losses equal to the switching losses. choose a low-side mosfet (n l ) that has the lowest possible on-resistance (r ds(on) ), comes in a moder- ate-sized package (i.e., so-8, dpak, or d 2 pak), and is reasonably priced. ensure that the max1533/MAX1537 dl_ gate driver can supply sufficient current to support the gate charge and the current injected into the para- sitic drain-to-gate capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction prob- lems may occur. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the step-down topology. power-mosfet dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at minimum input voltage: generally, use a small high-side mosfet to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissi- pation limits often limits how small the mosfet can be. the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high-side switching losses do not become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfets (n h ) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influ- ence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching loss cal- culation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably includ- ing verification using a thermocouple mounted on n h : where c rss is the reverse transfer capacitance of n h , and i gate is the peak gate-drive source/sink current (1a typ). pd n switching vcfi i h in max rss sw load gate ( ) () = () 2 pd n sistive v v ir h out in load ds on ( re ) () = ? ? ? ? ? ? () 2 figure 10. input rms current input capacitor rms current vs. input voltage v in (v) i rms (a) 18 16 12 14 10 8 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 620 in phase 5v/5a and 3.3v/5a 50/50 interleaving 40/60 optimal interleaving input rms current for interleaved operation input rms current for single-phase operation (i out5 - i in ) 2 (d lx5 - d ol ) + (i out3 - i in ) 2 (d lx3 - d ol ) + (i out5 + i out3 - i in )2 d ol + i in 2 (1 - d lx5 - d lx3 + d ol ) d lx5 = v out (v in - v out ) v in i rms = i load d ol = duty-cycle overlap fraction v out5 v in d lx3 = v out3 v in ( ) i rms =
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 33 switching losses in the high-side mosfet can become a heat problem when maximum ac-adapter voltages are applied, due to the squared term in the switching- loss equation (c x v in 2 x f sw ). if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy-overload conditions that are greater than i load(max) but are not high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, ?verdesign?the cir- cuit to tolerate: where i limit is the peak current allowed by the current- limit circuit, including threshold tolerance and sense- resistance variation. the mosfets must have a relatively large heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward-voltage drop low enough to prevent the low-side mosfet? body diode from turning on during the dead time. as a general rule, select a diode with a dc current rating equal to 1/3rd the load current. this diode is optional and can be removed if efficiency is not critical. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate-charging requirements of the high-side mosfets. typically, 0.1? ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1?. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets?gates: where q gate is the total gate charge specified in the high-side mosfet? data sheet. for example, assume the fds6612a n-channel mosfet is used on the high side. according to the manufacturer? data sheet, a sin- gle fds6612a has a maximum gate charge of 13nc (v gs = 5v). using the above equation, the required boost capacitance is: selecting the closest standard value. this example requires a 0.1? ceramic capacitor. applications information duty-cycle limits minimum input voltage the minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the electrical characteristics table). however, keep in mind that the transient performance gets worse as the step-down regulators approach the dropout volt- age, so bulk output capacitance must be added (see the voltage sag and soar equations in the design procedure section). the absolute point of dropout occurs when the inductor current ramps down during the off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). this results in a minimum operating voltage defined by the following equation: where v chg and v dis are the parasitic voltage drops in the charge and discharge paths, respectively. a rea- sonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. maximum input voltage the max1533/MAX1537 controllers include a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the electrical characteristics table). operation above this maximum input voltage results in pulse-skipping operation, regardless of the operating mode selected by skip . at the beginning of each cycle, if the output voltage is still above the feed- vvvh d vv in min out chg max out dis () =+ + ? ? ? ? ? ? + () 1 1 - c nc mv f bst == . 13 200 0 065 c q mv bst gate = 200 ii i load limit inductor = ? ? ? ? ? ? - ? 2 pd n sistive v v ir l out in max load ds on ( re ) () ( ) = ? ? ? ? ? ? ? ? ? ? ? ? ? ? () 1 2 -
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 34 ______________________________________________________________________________________ back-threshold voltage, the controller does not trigger an on-time pulse, effectively skipping a cycle. this allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. this results in an input threshold voltage at which the controller begins to skip pulses (v in(skip) ): where f osc is the switching frequency selected by fsel. pc board layout guidelines careful pc board layout is critical to achieving low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 11). if possible, mount all of the power compo- nents on the top side of the board, with their ground terminals flush against one another. follow these guide- lines for good pc board layout: keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance caus- es a measurable efficiency penalty. minimize current-sensing errors by connecting csh_ and csl_ directly across the current-sense resistor (r sense_ ). when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (ref, fb_, csh_, csl_). layout procedure 1) place the power components first, with ground termi- nals adjacent (n l _ source, c in , c out _, and d l _ anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet, preferably on the back side opposite n l_ and n h_ to keep lx_, gnd, dh_, and the dl_ gate- drive lines short and wide. the dl_ and dh_ gate traces must be short and wide (50 to 100 mils wide if the mosfet is 1 inch from the controller ic) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) group the gate-drive components (bst_ diode and capacitor, ldo5 bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figures 1 and 11. this diagram can be viewed as having two separate ground planes: power ground, where all the high-power compo- nents go; and an analog ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly at the ic. 5) connect the output power planes directly to the out- put-filter-capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the load as is practical. vv ft in skip out osc on min () () = ? ? ? ? ? ? 1
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 35 figure 11. pc board layout via to power ground max1533 top layer max1533 bottom layer via to ref bypass capacitor connect gnd and pgnd to the controller at one point only as shown connect the exposed pad to analog gnd inductor c out c out c in input kelvin-sense vias under the sense resistor (see the evaluation kit) ground output inductor c out c in input ground output dh lx dl high-power layout low-power layout dual n-channel mosfet single n-channel mosfets via to ref pin via to v cc bypass capacitor via to v cc pin
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers 36 ______________________________________________________________________________________ chip information transistor count: 6890 process: bicmos csl5 fb5 dl5 pgnd fb3 csl3 dl3 ldo3 ldo5 on3 ona fsel ilim5 ref gnd adja 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 dh3 bst3 lx3 csh3 uvp pgood pgdly v cc ina shdn skip dh5 bst5 lx5 in csh5 ldoa thin qfn 6mm x 6mm MAX1537 top view ilim3 ovp on5 pin configurations (continued)
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers ______________________________________________________________________________________ 37 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l c c l k k l l detail b l l1 e xxxxx marking f 1 2 21-0140 package outline, 16, 20, 28, 32l thin qfn, 5x5x0.8mm -drawing not to scale- common dimensions 3.35 3.15 t2855-1 3.25 3.35 3.15 3.25 max. 3.20 exposed pad variations 3.00 t2055-2 3.10 d2 nom. min. 3.20 3.00 3.10 min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-1, t2855-3 and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec t1655-1 3.20 3.00 3.10 3.00 3.10 3.20 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 3.10 t3255-2 3.00 3.20 3.00 3.10 3.20 2.70 t2855-2 2.60 2.60 2.80 2.70 2.80 l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 down bonds allowed no yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3.20 3.00 3.10 no no no no no no no no yes yes yes yes 3.20 3.00 t1655-2 3.10 3.00 3.10 3.20 yes no 3.20 3.10 3.00 3.10 t1655n-1 3.00 3.20 3.35 3.15 t2055-5 3.25 3.15 3.25 3.35 y 3.35 3.15 t2855n-1 3.25 3.15 3.25 3.35 n 3.35 3.15 t2855-8 3.25 3.15 3.25 3.35 y 3.20 3.10 t3255n-1 3.00 no 3.20 3.10 3.00 l 0.40 0.40 ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** see common dimensions table 0.15 11. marking is for package orientation reference only. f 2 2 21-0140 package outline, 16, 20, 28, 32l thin qfn, 5x5x0.8mm -drawing not to scale- 12. number of leads shown are for reference only.
max1533/MAX1537 high-efficiency, 5x output, main power-supply controllers for notebook computers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 38 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l e 1 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm l1 l e 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220, except for 0.4mm lead pitch package t4866-1. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. e 2 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm

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